Software-based Electronic Design Automation (EDA) tools, in general, can process circuit designs through what is referred to as an implementation flow to implement the circuit design within a given target programmable logic device (PLD). A circuit design can be specified in programmatic form, e.g., as a netlist, as one or more hardware description language files, or the like. A typical implementation flow entails various phases, or stages, such as synthesis, translation, packing, placement, and routing. The resulting circuit design is transformed into a bitstream that, when loaded into the target PLD, configures the target PLD to implement the circuit design.
Modern EDA tools also support iterative implementation flows. An iterative implementation flow is characterized by more than one pass through one or more or all phases of an implementation flow. Within an iterative implementation flow, the EDA tools must be able to process an existing implementation or a partial implementation of the circuit design. Typically, after a first pass through one or more phases of an implementation flow, the user makes some change to the existing circuit design. Such a change can include, but is not limited to, an HDL change, a timing requirement change, a physical packaging change, a physical floor-planning change, a design attribute change, etc. The circuit design is re-implemented in that it is processed through one or more of the phases of the implementation flow such that the changes are applied to the existing implementation, whether whole or partial, of the circuit design. That is, the changes are applied to a version of the circuit design that was generated from a prior implementation flow or phase of an implementation flow.
Examples of iterative implementation flows can include, but are not limited to, guide exact flow, guide leveraged flow, incremental design flow, and modular design flow. These examples of iterative implementation flows are supported by various software implementation tools available from Xilinx, Inc. of San Jose, Calif. (Xilinx® is a trademark of Xilinx, Inc. in the United States, other countries, or both.) Guide exact flow, for example, attempts to incorporate circuit design changes into the existing circuit design while preserving as much of the previous implementation of the circuit design as possible. Typically, the unchanged portions of the circuit design are “locked” throughout the re-implementation process.
Guide leverage flow refers to a process in which circuit design changes are incorporated into the existing circuit design, but implementation, or re-implementation, runtime is minimized. Runtime minimization usually entails taking the unchanged portions of the circuit design as the starting point and allowing changes to be applied to the circuit design, including the unchanged portions, as needed to implement the specified changes.
Incremental design flow refers to a process that combines objectives of guide exact and guide leverage flows into a single flow. In an incremental flow, the circuit design is divided into smaller pieces referred to as “partitions”. For each partition that is not affected by a “current” change, the EDA tool re-applies the previous implementation of that partition. The EDA tool may alter the previous implementation of various partitions to the extent permitted by user assigned attributes associated with each respective partition of the circuit design.
Modular design flow refers to a divide-and-conquer technique in which a circuit design is subdivided, or partitioned, into a plurality of sub-designs. Each sub-design can be implemented independently of the others. This approach is suited for team environments in which different teams of developers are tasked with developing different sub-designs.
In each of these iterative implementation flow examples, the EDA tool must process an implemented, or partially implemented, circuit design into a feasible circuit design, i.e., one that can be successfully implemented on a target PLD. To this extent, other circuit design techniques also can be viewed as iterative implementation flows. For example, the inclusion of hard macros which specify placed and routed components, into a circuit design may be considered a type of iterative implementation flow.
Most PLDs, for example field programmable gate arrays, are constrained with respect to the number, or amount, of circuit resources that can be provided. Such constraints stem from a variety of factors including overall chip area. As a result, there typically is a large number of wires versus the number of available programmable interconnect points (PIPs) on a device. This means that each wire on the PLD cannot connect to each other wire on the PLD. Instead, wiring connectivity is carefully designed to maximize connectivity and circuit performance through the limited number of PIPs that are provided.
Limited routing connectivity associated with PLDs can create a number of circuit design challenges that EDA tools must address in order to generate feasible, routed, circuit designs. For example, limited routing connectivity influences the placement phase of an implementation flow, particularly in the context of iterative implementation flows.